The Intel Xeon E5 is one of the most popular CPUs used in server platforms. Let’s use an Intel Xeon E5 v2 (Ivy Bridge) as an example. Therefore in certain configurations, DIMMs will run slower than their listed maximum speeds. And as more ranks are used in a memory channel, memory speed drops restricting the use of additional memory. As more ranks per DIMM are used the electrical loading of the memory module increases. As shown in Table 1, using more physical ranks per channel lowers the clock frequency of the memory banks. Unfortunately, there is a downside when aiming for high memory capacity configurations and that is the loss of bandwidth. Part 6: NUMA Architecture and Data Locality This topic amongst others will be covered in the upcoming FVP book. This is a series of articles that I wrote to share what I learned while documenting memory internals for large memory server configurations.
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